Research on Plasma Noise Suppression in High-Voltage Power Supplies for Etching Equipment

Plasma noise is a core interference source in semiconductor etching processes, manifesting as power output fluctuations, electromagnetic radiation, and abnormal discharges. These phenomena directly impact etch uniformity, selectivity, and device yield. The fundamental cause lies in transient impedance mismatch of plasma loads, leading to energy reflection and resonant distortion. As technology nodes advance to the nanoscale, noise suppression has become a critical challenge in high-voltage power supply design, requiring multi-dimensional optimization of physical mechanisms, power topologies, and control strategies. 
1. Noise Generation Mechanisms and Impacts
Plasma noise primarily originates from three physical processes: 
• Nonlinear Sheath Oscillation: Under high-frequency power excitation (>27 MHz), the thickness of the plasma sheath at the electrode surface fluctuates with ion flux variations, causing abrupt RF reflected power changes and harmonic distortion in power supply output current. 
• Electron Bounce Discharge: During pulsed modulation, if DC bias is applied prematurely upon high-frequency power initiation, electrons bouncing in an unstable sheath electric field can trigger abnormal arc discharges at the upper electrode, generating electromagnetic pulse noise. 
• Gas Ionization Instability: Reactive gases (e.g., SF₆/CF₄ mixtures) exhibit abrupt avalanche ionization rate changes due to local pressure or temperature gradients during high-voltage ionization, leading to plasma density oscillations and periodic impedance disturbances. 
Experiments show that reflected power exceeding ±0.5% results in up to 8% etch depth variation across wafers, while high-frequency noise (>100 kHz) may cause RF matching network overheating failures. 
2. Timing Control for Bounce Discharge Suppression
Precise coordination of high-frequency and DC bias timing blocks electron bounce paths: 
• Delayed Voltage Application: During the initial period (1–5 μs) after high-frequency power initiation, DC negative voltage to the upper electrode is suspended until the sheath electric field stabilizes. Low-amplitude DC voltage (e.g., -500 V) is then applied, while high-amplitude negative voltage (e.g., -2 kV) is injected during high-frequency off-periods to accelerate electron penetration into deep structures. 
• Duty Cycle Optimization: Experiments identify an optimal voltage suspension period of 15–20% of the pulse cycle, balancing discharge suppression and ion neutralization efficiency. Exceeding 30% reduces etch rates by over 12% due to ion flux loss. 
3. Resonant Conversion and Dynamic Impedance Matching
Advanced power topologies significantly reduce inherent noise: 
• SiC-Based Resonant Circuits: Silicon carbide (SiC) MOSFETs construct LCC series-parallel resonant networks, elevating switching frequencies beyond 100 kHz and reducing switching losses by 70%. This approach minimizes high-frequency harmonics at the source. Zero-voltage switching (ZVS) technology further suppresses current spikes induced by arc discharges. 
• Dual-Mode Closed-Loop Control: Combining pulse width modulation (PWM) and pulse frequency modulation (PFM) maintains fixed-frequency variable-pulse-width operation under stable loads, while switching to fixed-minimum-pulse-width variable-frequency during load transients. For example, in diamond etching, real-time reflected power monitoring dynamically tunes matching network capacitance, suppressing power reflection below 0.3%. 
4. Electromagnetic Compatibility Enhancement
• Three-Stage Filtering Architecture: Input power stages deploy π-filters (attenuating <100 kHz noise), common-mode chokes (suppressing MHz interference), and ferrite cores (absorbing GHz radiation), collectively reducing electromagnetic interference (EMI) by over 40 dB. 
• Shielding and Grounding: Double-layer copper braided shields enclose high-voltage cables, sharing grounding points with plasma chambers to eliminate ground loop potential differences. Differential signaling in communication lines improves common-mode noise rejection by 20-fold. 
5. Emerging Technology Trends
• AI Predictive Control: Long short-term memory (LSTM) models trained on plasma emission spectra predict impedance mutation points, enabling proactive power parameter adjustments to minimize reflected power overshoot during process transitions. 
• Nanosecond Pulsing: Pulse widths compressed below 200 ns control ion energy distribution bandwidth (ΔEi<5 eV), suppressing broadband noise induced by nonlinear sheath oscillations. 
Conclusion
Plasma noise suppression marks a pivotal transition in high-voltage power supply design—from energy transmission to precision energy control. Future advancements require deeper exploration of noise coupling mechanisms with plasma chemical reactions and the development of power architectures with ultra-low electromagnetic emissions, sub-microsecond response, and multi-scale impedance adaptability, ultimately supporting 3D IC and quantum device manufacturing.