Multi-Physical Field Co-Simulation for High-Voltage Power Supply of Electrostatic Chucks

Abstract: 
As semiconductor manufacturing advances toward sub-nanometer precision, the voltage stability and thermal management performance of electrostatic chucks (ESC) become critical for wafer deformation control. This study employs multi-physics co-simulation to systematically analyze the coupling mechanism of electrostatic-thermal-structural fields in ESCs under high-voltage (0.5-5kV) excitation, providing theoretical foundations for power topology design and process optimization. 
1\. Multi-Physical Field Coupling Mechanism
The high-voltage power system for ESCs must simultaneously fulfill three core requirements: 
• High-voltage accuracy: Voltage ripple <0.1% at 5kV operation 
• Dielectric loss control: tanδ of ceramic layer <1×10⁻³ 
• Transient thermal response: Temperature gradient <0.3°C/s under step voltage 
Numerical simulations reveal that when 2kV DC bias is applied, gradient electric fields (peak 12kV/mm) form in Al₂O₃-Ti composite layers, inducing space charge accumulation. Joule heating from charge migration creates localized temperature spikes (Fig.1), generating 12°C hot spots at electrode edges that cause 85nm wafer deformation—exceeding tolerance thresholds for advanced nodes. 
2\. Key Simulation Technologies
A 3D fully-coupled model in COMSOL Multiphysics establishes: 
(1) Electrostatic Governing Equation: 
∇·(ε_r ε_0 ∇V) = -ρ_v 
with space charge density ρ_v affected by carrier mobility μ: 
ρ_v = σ(E) × exp(-E_a/kT) 
(2) Electro-Thermal Coupling: 
Dielectric loss power density: 
P_d = 2πf ε_0 ε_r E_rms² 
Thermal boundary conditions incorporate plasma radiation (500W/m²) and coolant convection (h=1800 W/(m²·K)) 
(3) Structural Mechanics: 
Thermal stress tensor: 
σ_ther = α E ΔT / (1-2ν) 
Coupled with electrostrictive stress σ_es = -ε_0 ε_r E² /2 
3\. Power Supply Optimization Verification
Parametric scanning yields optimization pathways: 
Parameter Baseline Optimization Deform. Reduction
Voltage rise time 50ms 5ms 34.7%
Frequency stability ±500ppm ±5ppm 28.2%
Electrode curvature 0.1mm 0.5mm 41.5%
 
Optimizing electrode geometry from hexagonal to gradient-spiral topology reduces electric field non-uniformity from 0.38 to 0.11, improving wafer clamping force consistency by 62%. Pulse-type thermal compensation with 55Hz AC voltage during etch idle time compresses wafer temperature fluctuation from ±1.2°C to ±0.3°C. 
4\. Experimental Validation & Industrial Value
300mm wafer tests confirm that a dual-polarity power supply (positive voltage + negative bias compensation) designed per simulations achieves in 3nm critical layers: 
• Wafer deformation: Reduced from 125nm to 42nm 
• Defect density: Decreased by 1.8/cm² 
• Ionic contamination: Na⁺ contamination <1×10¹⁰ atoms/cm² 
Conclusion: 
Multi-physics co-simulation for ESC high-voltage power systems elucidates interactions between electric field distortion, dielectric heating, and mechanical stress. Implementing space charge compensation algorithms, gradient electrodes, and active thermal control during power design significantly enhances yield in advanced semiconductor processes. This methodology demonstrates substantial value for domesticating ultra-precision manufacturing equipment.