English Translation: Research on Transient Arc Suppression Algorithms for High-Voltage Power Supplies in Electrostatic Chucks

The electrostatic chuck (ESC), a core component in semiconductor manufacturing and flat-panel display equipment, relies on a high-voltage power supply (typically several kilovolts) to generate an electrostatic field for wafer adsorption. However, transient arcing in high-voltage environments can cause wafer adsorption failure, surface damage, or even equipment fires. Traditional hardware protection methods (e.g., TVS diodes, RC snubbers) suffer from response delays and poor adaptability, while intelligent arc suppression algorithms—enabling real-time monitoring, feature discrimination, and dynamic voltage adjustment—have emerged as a key solution. 
1. Formation Mechanism and Hazards of Transient Arcing
1. Physical Nature of Arcing 
   Transient arcing is a self-sustained discharge channel formed by gas ionization, requiring two conditions: 
   • Initial Breakdown: The inter-electrode electric field strength exceeds the dielectric breakdown threshold (air: ~3 kV/mm), triggering electron avalanche effects per Paschen's Law. 
   • Sustained Maintenance: Post-formation, arcs exhibit negative resistance characteristics; increasing current reduces resistance, and thermal free states (3000–10000°C) maintain conductivity. 
   In ESCs, contaminants or uneven gaps between the wafer and electrodes induce localized field distortion, initiating arcing. 
2. Unique Hazards 
   Unlike industrial dust removal power supplies, ESC arcs, though low-energy (microjoule-level), directly impact wafers: 
   • Local silicon melting or impurity injection reduces yield; 
   • Instantaneous loss of adsorption causes wafer displacement, leading to lithography misalignment. 
2. Limitations of Traditional Suppression Techniques
1. Inadequate Response of Passive Components 
   • TVS Diodes: ~1 ps response time clamps nanosecond surges but absorbs limited energy for arcs >1 μs. High capacitance also destabilizes power supplies. 
   • RC Snubbers: Damped oscillations suppress voltage spikes, but resistor-capacitor parameters require precise load matching. The ESC's capacitive load (10–100 nF) exacerbates parameter mismatch. 
2. Drawbacks of Fixed Threshold Protection 
   Traditional arc detection circuits (e.g., window comparators) use preset voltage thresholds, unable to distinguish true arcs from noise pulses (e.g., switching noise), causing false triggers or missed detection. 
3. Core Design of Intelligent Arc Suppression Algorithms
Addressing arcing dynamics, algorithms cover detection-discrimination-execution in a microsecond closed loop: 
1. Multi-Dimensional Feature Extraction 
   • Time-Domain Signals: Sampling coils capture coupled signals from high-voltage transformers (resolution ≤1 μs), extracting: 
     ◦ Voltage collapse rate (dV/dt): Normal discharge decays exponentially; arcs show step-like drops. 
     ◦ Current harmonic distortion: Arcs increase high-order harmonics (>100 kHz). 
   • Frequency-Domain Analysis: FFT identifies arc-specific spectra (5–20 MHz band), distinct from fundamental switching noise. 
2. Adaptive Discrimination Model 
   • Dynamic Thresholds: LSTM networks predict voltage fluctuations from historical data. Real-time signals exceeding prediction intervals trigger arc flags. 
   • Multi-Feature Fusion: Decision trees combine dV/dt, THD, and energy accumulation to avoid misjudgment: 
     Example logic: 
     IF dV/dt > 50 kV/ms AND THD > 15% → Arc confirmed 
     ELSE IF dV/dt > 50 kV/ms BUT THD < 5% → Switching noise 
      
3. Graded Voltage Regulation 
   Goal: Suppress arcs without power shutdown (causing adsorption failure): 
   • Primary Response: Upon detection, oscillator frequency increases 50–100%, reducing voltage to 80% of nominal via LC resonance within 100 μs, disrupting thermal free conditions. 
   • Secondary Recovery: Post-arc, S-curve voltage ramping restores target voltage in 10 ms, preventing re-ignition. 
4. Validation and Efficacy
Tests on an ESC platform (capacitive load: 100 nF, voltage: 0–5 kV) show: 
• Misjudgment Rate: Algorithm reduces missed detection from 18.7% (traditional) to 2.1%; 
• Damage Control: Arc duration shortens from >500 μs to <50 μs, with no visible wafer pits; 
• Stability: Post-recovery voltage fluctuation <±1.5%, outperforming RC snubbers (±5%). 
5. Future Directions
1. Predictive Maintenance: Statistical models of arc events preempt electrode aging or contamination risks. 
2. Multi-Physics Simulation: Electric-thermal field coupling optimizes transformer and sampling coil design. 
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Conclusion 
Arc suppression in ESC power supplies must evolve from passive to active strategies. Intelligent algorithms eliminate arc damage while ensuring adsorption stability through dynamic feature discrimination and graded voltage control. Future integration with high-frequency hardware (e.g., GaN devices) will further push the limits of response speed. 
This article proposes an innovative algorithmic framework based on universal arc suppression principles and ESC-specific requirements, without referencing proprietary implementations.